1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a technology for controlling a command decoder that decodes a command inputted to a semiconductor device.
2. Description of the Related Art
A memory device performs diverse operations such as an active operation, a read operation, a write operation, a precharge operation, and a refresh operation in response to command signals received from an external memory controller. A circuit for decoding the command signals that are inputted from the source other than the memory device is referred to as a command decoder, which is described below.
FIG. 1 illustrates a structure related to a command decoder in a conventional memory device.
Referring to FIG. 1, the memory device includes pads 101 to 105, buffers 111 to 115, and a command decoder 120.
The pads 101 to 104 receive command signals RASB, CASB, WEB and CSB from the outside of the memory device, and the buffers 111 to 114 buffer the command signals RASB, CASB, WEB and CSB that are applied to the pads 101 to 104. The command signals include a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and a chip selection signal CSB. The symbol ‘B’ at the end of the command signals RASB, CASB, WEB and CSB represent that the signals are enabled to a logic low level.
The pad 105 receives an external clock CLK from the outside of the memory device, and the buffer 115 buffers the clock CLK, which is applied to the pad 115.
The command decoder 120 generates internal commands MRS, ACTIVE, WRITE, READ, REFRESH and PRECHARGE by decoding the command signals RASB, CASB, WEB and CSB in synchronization with the clock CLK. The internal commands include a mode register set command MRS, an active command ACTIVE, a write command WRITE, a read command READ, a refresh command REFRESH, and a precharge command PRECHARGE.
The command decoder 120 decodes the command signals RASB, CASB, WEB and CSB in synchronization with the clock CLK whenever the clock CLK toggles. In other words, there is a concern that the command decoder 120 continues to consume current whenever the clock CLK toggles. Therefore, there is a need to develop a technology that may reduce the amount of current consumed in the command decoder 120.